1. Field of the Invention
This invention relates to an input/output device for use in conjunction with a microprocessor unit and more specifically to a one chip semiconductor device input/output unit.
2. Description of the Prior Art
Recent advances in the semiconductor art have included the development of a number of LSI semiconductor circuits commonly referred to as microprocessors. One such unit is the Model TMS 8080 microprocessor available from Texas Instruments Incorporated of Dallas, Texas. The TSM 8080 is an eight bit parallel central processing unit fabricated on a single chip using a high speed N-channel silicon gate process. A complete microcomputer system can be formed by interfacing this circuit with any appropriate memory. Microprocessors such as the TMS 8080 provide powerful computational capability at a low cost and in a very small package. They are useful in a wide variety of applications, one class of such applications being as the central controller in any of various types of real time electronic systems.
When utilized in a real time system, however, it is necessary to provide circuits for interfacing the microprocessor with the other hardware units of the system. For example, the TMS 8080 microprocessor has an eight bit parallel bidirectional data bus. It is necessary to provide controlled buffering means for synchronizing the parallel transfer of data words between the microprocessor and other system elements. Further, in many of the systems wherein a microprocessor may find use, certain of the system elements will require that the bits of a data word be transferred in serial rather than in parallel fashion. Accordingly, it is necessary to provide structure for accepting a data word from the parallel data bus and transmitting the bits serially, and for accepting incoming data words serially into a buffer to be ultimately shifted onto the parallel data bus. Preferably the serial data transfer may occur at any of a pluraity of selectable baud rates as required by the microprocessor. It is also desirable in many cases to provide the microprocessor with one or more external interval timers. The microprocessor directs an interval timer to begin counting at some point in time and at the expiration of a preselected time interval the timer responds to inform the microprocessor that the time interval has expired. Further, it is necessary to provide means for generating interrupt messages to inform the microprocessor of the existence of certain conditions in the other elements of the system. The expiration of one of the interval timers, for example, may be communicated by means of an interrupt signal. Preferably the various interrupts will be maskable and will be recognized by the microprocessor in accordance with a predetermined priority arrangement.
In the past it has been known to provide one or more of the above-mentioned interface functions by random logic networks typically comprising a large number of TTL intergrated circuits. This type is implementation, however, is undesirable for several reasons. The large number of integrated circuits occupy a large printed circuit board area and prevent the desired miniaturization of the system. Further, the power required by the integrated circuits requires large power supplies, again in conflict with the interest in miniaturization. The design of a custom combination of integrated circuits for each new application requires the dedication of a large amount of engineering time. Further, once designed the system is highly inflexible and not readily amenable to modifications. An important consideration in a system comprised of a plurality of integrated circuits is the large amount of time and effort required to assemble each such system.
There is commercially available an LSI semiconductor device for generating interrupt signals. The interrupts of this device are not maskable. Even if this device is incorporated in a microprocessor controlled system, it would be necessary to provide the plurality of TTL type circuits for the masking function as well as the other previously enumerated functions (synchronized parallel I/O, serial I/O, interval timers).